In your new role you will:​

• Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

• Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

• Execute the verification plan by developing C/C++ test cases and System Verilog/UVM testbench components and by integrating 3rd party VIP components.

• Simulate and debug at RTL, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure.

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For a more senior role, you will also:

• Lead a team technically through exploring new environments and identifying potential enhancement areas through new methodology.

• Identify and set mid/long-term goals based on benchmarking against industry standards.

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Requirements:​

• Masters/Bachelors in Electrical Engineering or Computer Science with 5-12 years of relevant work experience.

• Strong foundational knowledge of digital design & verification.

• Advanced knowledge and hands-on experience of System Verilog and UVM.

• Hands-on experience in hardware-software debugging at the system or application level. Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills is a plus

• Exposure to version-controlling (eg, Git/Bitbucket, Clearcase, CVS, SVN) and bug-management schemes

• Dynamic and energetic with zero verification escape mindset

• Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.

• Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives.

• Knowledge on ISO26262 and ISO21434 are advantageous.

• Verification experience in COM, CPU peripherals, BUS or pattern development is a plus. Experience in testbench/verification environment set up is also a plus.

• A candidate who has more relevant working experience will be considered for a more senior position

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DISCLAIMER

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

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We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 semicon@hpspartners.com.sg 

 

We regret that only shortlisted candidates will be contacted for a discussion.