In your new role you will:​

• Responsible to deliver high-quality RTL coding, verification and synthesis on area of work.

• Responsible for the concept, DFT and design of the IP assigned.

• Tightly working with SOC Layouters and the analog/software team.

• Perform full pre and post-layout IP and Fullchip verifications.

• Implement digital design in FPGA and perform the FPGA debugging.

• Exposure to all stages of IC Design processes and flow.

• Continuous improvement on digital design methodologies and flow.

• Define silicon bring up plan and component validation of 1st silicon.

• Define IP /Chip micro-architecture for design reviews in the project.

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Requirements:​

• Good knowledge in digital design techniques and the state-of-the-art design verification method.

• Solid fundamentals in IC design flow and verification concepts.

• Experience with RTL2GDS, floorplanning, static timing analysis, timing closure and verification

• Hands-on exposure on of FPGA, formal verification and power analysis.

• Knowledge in ACDC SMPS IC design-related will be an advantage.

• Good in scripting using PERL/PYTHON

• Exposure to Cadence and Synopsys tools

• Experienced in DFT scan tools and test mode concepts will be an advantage.

• Able to communicate well and good in interpersonal skills

• Strong analytical and problem-solving skills

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DISCLAIMER

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

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We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 semicon@hpspartners.com.sg 

 

We regret that only shortlisted candidates will be contacted for a discussion.