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Principal Engineer - Digital Design

In your new role you will:

  • Close cooperation with Concept Engineering to lead IP feasibility studies and to develop new IPs based on customer requirements for digital content.

  • Define the concept and requirements of the digital block architecture for the mixed signal IPs mainly for sensors; eg PVT sensors, temperature sensors and another type of sensors;

  • Translate IP concept and design requirements into RTL design

  • Perform RTL design, specifying design constraint and executing the entire design flow as in LEC, Spyglass Linting, CDC RDC to meet the quality requirements.

  • Support R2G flow and activities guaranteeing that RTL code is synthesizable and meeting the signoff requirements;

  • Generate Design Documentation Reports and actively participate in Design Reviews;

  • Drive risk assessment, risk management and Design FMEAs in mixed signal IP development;

  • Drive preparation of IP level verification and validation plans as well working with Test Engineers in defining the mixed signal IPs test plan;

  • Support mixed signal IPs validation and debugging activities with Product, Quality and Test Engineering up to production ramp-up;

  • Drive methodology changes in the area of Digital Design and Digital Functional Verification but also in the cross-discipline areas with Analog Design

  • Take ownership and support the design in the adjacent disciplines, especially Digital  Functional Verification, Firmware, Component Verification until it reaches the customer

  • Main technical person in driving innovation of the digital contents for the mixed signal IPs.

  • Provide mentorship and coaching to team members and to provide support if required.


  • A Master Degree or Ph.D. in Electronic Engineering or similar field of studies with specific knowledge of microelectronic devices and related digital circuit design

  • Solid experience in digital design implemented on sub-micron technologies;

  • At least 10 years of experience in digital design implementation with excellent knowledge of RTL coding using Verilog or SystemVerilog

  • A good command of behavioral modeling using SystemVerilog, Matlab or equivalent

  • At least 4 years of experience as a Technical Lead or have taken the role as a mentor;

  • Solid knowledge of multiple power domains design using UPF/CPF and multiple clock domains;

  • In-depth knowledge of Unix OS and scripting languages, such as Perl and Python

  • Excellent knowledge of IC design and verification tools (Cadence, Synopsys)

  • Experience in complete RTL to GDS flow

  • Fluency in English (mandatory).

  • It is an advantage if you have:

    • Knowledge of analog & mixed-signal IC architectures and integration requirements;​

    • Experience in UVM methodology

    • Knowledge in signal processing and digital filters as in CIC, FIR and IIR.

    • Knowledge of Requirements Management methodologies

    • Experience with automotive standards in particular with ISO26262


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 


We regret that only shortlisted candidates will be contacted for a discussion.

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