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RTL Design Senior Engineer


  • Digital ISP IC design and verification.

  • Digital ISP IP development.

  • RTL design and integration of SoC architectures.

  • SoC and ISP IP integration and verification.

  • ISP implementation on FPGA.

  • Simulate RTL at the block level and SoC level to guarantee design functionality.

  • Synthesis and timing check at SoC level.

  • Define system and block level verification plans and test patterns.

  • Support the development of product requirements and specifications.



  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science or related field.

  • Solid knowledge of IC design fundamentals.

  • FPGA, Verilog, System Verilog, RTL, Digital Design.

  • 5+ years of experience in digital IC design.

  • Experience in ISP/Computer vision.

  • Experience in FPGA implementation and verification.

  • Have familiarity with MCU structure and peripheral design.

  • Strong background in SoC/IP design, integration and verification.

  • Superior analytical, problem-solving skills and teamwork spirit.


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 


We regret that only shortlisted candidates will be contacted for a discussion.

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