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Library Characterization Lead Engineer


  • Drive cell characterization, QA flows and setup collaterals for standard cells, memory and IOs.

  • Characterize and optimize standard cell libraries for FinFET technology, focusing on performance, power, and area metrics.

  • Collaborate with circuit designers and layout engineers to define library requirements and ensure adherence to design rules and guidelines.

  • Develop and execute test plans for standard cell library characterization, including timing, power, noise, and reliability analyses.

  • Conduct transistor-level simulations and circuit-level measurements to validate and optimize standard cell performance.

  • Perform detailed analysis of characterization data, identify deviations and anomalies, and propose corrective actions.

  • Work closely with process engineers to understand and mitigate process variations that may impact standard cell library performance.

  • Collaborate with the design automation team to enhance characterization methodologies and develop automation scripts for efficient library characterization.

  • Participate in technology node evaluations and provide recommendations for standard cell library optimizations based on technology roadmaps.

  • Collaborate with product development teams to ensure smooth integration and validation of standard cell libraries in advanced chip designs.

  • Stay up-to-date with the latest advancements in FinFET technology, standard cell design methodologies, and industry trends.


  • Bachelor’s degree in electrical engineering or a related field.

  • Extensive experience in standard cell library characterization, with a strong emphasis on FinFET technology.

  • Proficiency in industry-standard EDA tools for transistor-level and circuit-level simulations, such as Cadence or Synopsys and Cadence Virtuoso Liberate/LV/Mx/Trio.

  • Solid understanding of FinFET technology and its impact on standard cell library design and characterization.

  • Experience in characterizing standard cell libraries for advanced process nodes (e.g., 16nm, 12nm, 6nm or below) is highly desirable.

  • Knowledge of standard cell architectures, design rules, and layout considerations.

  • Familiarity with circuit and layout design, static timing analysis (STA) and power analysis methodologies.

  • Strong analytical skills and attention to detail for data analysis and problem-solving.

  • Excellent programming and scripting skills (e.g., Python, Perl, Tcl) for automation and data processing tasks.

  • Effective communication and teamwork skills to collaborate with cross-functional teams and present findings and recommendations.


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042

We regret that only shortlisted candidates will be contacted for a discussion.

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