• Derive the design micro-architecture from IP analog DFT specifications and requirements.

• Work with design, verification, SoC implementation and DFT teams across all sites of Infineon.

• Be a part of analog DFT execution team to develop design test solutions for common mixed-signal analog design IPs.

• Co concept/design implementation reviews.

• Perform digital design frontend implementation (Linting, synthesis...) checks to prove the implementability of the design.

• Documentation of module specification, verification simulation plan and simulation results in compliance to development work-flow.

• Support lab design validation and characterization of the mixed signal IP.

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Requirements:

• A Bachelor's degree in electrical/electronics engineering or equivalent.

• 1-4 years of relevant work experience in digital RTL development. Familiar with digital design flow: from RTL, simulation, synthesis, STA to silicon tapeout design flow

• Ability to develop RTL code and understand how RTL will map to gate-level structures.

• Strong debugging skills, experience in test bench development and RTL verification.

• Good Scripting skill (Unix Shell, Perl or Python), good knowledge of Digital IP, microprocessor and SoC concepts will be an added advantage.

• Good team player, proficient in English and communication skills.

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DISCLAIMER

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

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We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 semicon@hpspartners.com.sg 

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We regret that only shortlisted candidates will be contacted for a discussion.