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Staff/Senior Staff Engineer - Digital Design


  • You will take designs through the complete development lifecycle from concept/study to silicon bring-up

  • Research and develop new communication DSP algorithms

  • Perform architectural studies to determine optimal hardware implementations of IP/SOC infrastructure, peripherals to meet product requirements

  • Develop and review detailed and concise architecture and design specification documents

  • RTL logic design of modules using Verilog HDL. Designs may include power and clock management units, IP subsystem, digital interfaces to analog functions, accelerators, filters, demodulators supporting various wireless and wired communication protocols.

  • Prepare and hold architecture, design and verification reviews with technical staff throughout project lifecycle

  • Perform logic synthesis, timing and power analysis to optimize designs

  • Pre-silicon verification utilizing various methodologies such as constrained random verification with block/subsystem/chip level UVM test benches, spice co-simulation of mixed signal blocks and FPGA emulation.

  • Validation/bring-up of designs on silicon, providing support to cross-functional teams.


  • M.S. or Ph. D in Electrical Engineering with minimum 5+ years of professional experience in digital CMOS IC design

  • Experience using Matlab or other high-level modeling language/tool for designing and evaluating communication systems and algorithms

  • Strong understanding of block and chip-level verification and emulation

  • Experience with logic simulators for both RTL and gate-level simulation, design/waveform browsers, and power analysis tools, Verilog RTL design preferably on DSP/math-centric designs

  • Experience in implementing and analyzing fixed-point DSP, numerical processing elements, RF transceiver functions and impairments will be a plus


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 

We regret that only shortlisted candidates will be contacted for a discussion.

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