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Lead Principal - Chip Verification (Methodology) Engineer 

  • Be part of the technical leadership team for Chip Verification Methodology in a multi-site organization

  • Support Chip Verification Architect and MEG (Methodology Expert Group) on defining Verification Methodology for Sub-System/Chip/System level verification

  • Define and implement the next generation of verification environment architecture and methodology development

  • Drive topics forward together by working with various internal and external experts (e.g. application, analog/digital/mixed-signal, software, patterns) as well as management

  • Actively participating and contributing in cross-functional collaboration with design, software and hardware teams across multiple design sites, to ensure a successful product delivery

  • Conduct regular stakeholder meetings to understand user needs through proof of concepts and ensure scalability

  • Enable early pilot projects and start collaborations with teams with similar challenges

  • Lead methodology projects until deployment and ensure their continuity

  • Harmonize workflow and data flows for verification engineering methodologies and tools

  • Own and create technical tools/ documentation and ensure ISO26262 and ISO21434 compliance

  • Represent technical competence in Chip Verification Methodology and act as technical leader by active sharing your knowledge

  • Be the interface between user community representatives, methodology development and standardization committees for automotive standards


  • Masters/Bachelors in Electrical/Electronic Engineering with 15+ years of relevant work experience in highly complex Chip Development, ideally some insights into MCU, MPU, FinFET and SiP.

  • Strong foundational knowledge of digital/analog design & verification.

  • Substantial knowledge and hands-on experience of System Verilog and UVM.

  • Substantial knowledge in requirements engineering and related processes, methods, workflows, data flows

  • Hands-on experience on state of the art test benches development with scalability and automation

  • Experience in Network on Chip (NOC), AMBA, AHB/AXI and ARM are preferred.

  • Experience in low power and high-performance computing are preferred

  • Firmware/software experience is advantageous.

  • Top-level integration, RTL design, and synthesis experience are advantageous.

  • Experience in the automotive industry in functional safety and cybersecurity is a plus.

  • Details oriented with excellent written and verbal skills are required.


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 


We regret that only shortlisted candidates will be contacted for a discussion.

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