• Undertake a technical leadership position in Digital Verification at SOC.

• Execute SoC verification tasks and work closely with team members to review and understand the relevant functional and safety-related requirements.

• Write verification plans to meet these requirements after close alignment with other verification teams for proper work split according to mutually acceptable verification assignment.

• Execute the verification plan by developing Perspec or C/C++ test cases and SystemVerilog/UVM testbench components and by integrating 3rd party VIP components.

• Simulate and debug at RTL, Unit Delay, and Gate Level using appropriate tools and flows including Emulator, Portable Stimulus, or Formal methodologies for functional and toggle coverage closure.

• Leading a team technically through exploring new environments and identifying potential enhancement areas through the new methodology.

• Identify and set mid/long-term goals based on benchmarking against industry standards.

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Requirements:

• Masters/Bachelors in Electrical Engineering or Computer Science with min. 5 years of relevant work experience.

• Strong foundational knowledge of digital design & verification.

• Advanced knowledge and hands-on experience of SystemVerilog/UVM.

• Hands-on experience in hardware-software debugging at the system level. Hand-on experience with gate-level-simulations and with debugging/troubleshooting skills

• Exposure to version-controlling (eg, Git/Bitbucket, Clearcase, CVS, SVN) and bug-management schemes

• Dynamic and energetic with zero verification escape mindset

• Self-motivated, flexible, good communication with interpersonal skills and is a good team player who is able to work well with both internal and external partners.

• Candidate has proven ability to achieve results in a very dynamic, multi-site environment and be able to coordinate with priorities and self-initiatives.

• Candidate must have in-depth knowledge of microcontroller architecture and CLOCK/SRAM/RESET design and verification knowledge.

• Experience in the automotive industry for clocking modules like PLL, OSC and general clock related verification.

• Know-how of Portable Test and Stimulus Standard (PSS) with EDA tools like Perspec is a strong plus.

• Understanding of verifying bus protection schemes as well as memory bist controller will be useful.

• Candidate who has more relevant working experience may be considered for a more senior position.

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DISCLAIMER

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

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We invite interested candidates to write-in with CV in MS Word format to Lee Shiow Chyn, EA 12C6130/ R1112042. We regret that only shortlisted candidates will be contacted for a discussion.