​Responsibilities

• Makes a substantial contribution to the innovation of product and process. Develops new products, using the latest technologies and resources, often realizing systems based on  unverified specifications. 

• Execute the project on time and deliver results. 

• Manage the DOE/qualification lots and cycle time in SG site. 

• Perform Yield/FWT/AVI data analysis and troubleshooting. 

• Provide project regular update in DDD WW meeting. 

• Participate in project/technical discussions with DDD SJ design team and SG module team. New product introduction and coordinate/align with DDD WW team, SG Ops/engr, SJ epi team and L1 PG team.

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Requirements​

• Minimum Bachelors of Engineering with 4 to 7 years of semiconductor experience. 

• LED/semiconductor process technology and understanding in the areas of LED basic device physics 

• Wafer fab process basic knowledge (lithography, film deposition, cleaning &  dry/wet etching) 

• Yield/testing/defect screening analysis including FWT & AVILED L1 packaging basic  knowledge 

• Epitaxy-relevant technology (optional) 

• Deeper R&D experiences for die level developments (preference) 

• Micro-LED/multiple pixels LED development experience 

• Skilled in project management 

• Possess effective communication skills

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DISCLAIMER

The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

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We invite interested candidates to write-in with CV to Lee Shiow Chyn, EA 12C6130/ R1112042 semicon@hpspartners.com.sg 

 

We regret that only shortlisted candidates will be contacted for a discussion.