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Integration and Yield Manager


Job Type

Full Time, Permanent

Work Mode


Job description

  • Lead a team, oversee baseline team KPIs and task assignments, ensuring HOL improvements. 

  • Responsibilities include managing customer meetings, driving SPC and ECAP enhancements, and implementing the New F7 DOI SPC system.

  • Lead fab operations support by monitoring inline excursions, improving processes, and addressing tool defect performance. 

  • Collaborate with the defect team to analyze and characterize defects, and enhance defect monitoring and sampling methodologies.

  • Resolve manufacturing-related problems, train engineers, and adjust inspection strategies to achieve Excursion Free Manufacturing (EFM).

  • Represent the team at customer conferences, visits, and audits, and ensuring wafer quality meets standards.


  • Master’s or Bachelor’s Degree in Electrical / Electronics / Mechanical / Mechatronics / Microelectronics Engineering with at least 5-8 years of relevant experience in wafer fabrication industry

  • Proficiency in defect or yield improvement skills is essential.

  • Strong understanding of defect reduction strategy, defect to yield correlation methodologies, and current market defect solutions and roadmap.

  • Excellent interpersonal and communication skills.

  • Strong analytical and project management abilities.

  • Systematic and organized approach to problem-solving, with familiarity in SPC, DOE, and FMEA methodologies.


The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.

We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.

Lee Shiow Chyn

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