We are seeking experienced candidates who have a keen interest in circuit design, specifically in power management circuits, level shifters, retention flops, power switches, power delivery circuits, memory related circuits and other low power custom circuits. The ideal candidate will possess a strong understanding of CMOS device characteristics and design rules, as well as knowledge of deep submicron process issues and FinFET technologies.
In addition, the candidates should have a deep understanding of custom digital and analog circuits and optimization techniques for better power, performance, and area (PPA). The candidate should have experience in layout design and be able to optimize parasitics in various types of layouts. Furthermore, proficiency in scripting languages such as Perl, Python, and Tcl is a must. The candidate should also have hands-on experience running SPICE simulations and process variation analysis.
A thorough understanding of timing characterization and modeling of standard cell circuits is also important. The successful candidate will have excellent communication and analytical skills and be able to work effectively as part of a team. Overall, we are looking for a candidate who is passionate about circuit design and has the necessary skills and knowledge to excel in this role. If you are enthusiastic, detail-oriented, and possess the qualities we are seeking, we would love to hear from you.
Investigate, plan, and design and productize novel sub-threshold and near-threshold circuits and other related low power circuit techniques (e.g., adaptive body biasing, adaptive clock distributions, level shifters, customized standard cells, specialized memory structures, PDN modeling etc.).
Validate and refine low power circuit design techniques as part of a team that is building standard cells in advanced nodes (e.g., 12nm and beyond).
Work with product development teams (library characterization, Engineering, Architecture and Product Planning team) to rapidly deploy newly developed custom circuits and standard cells in products.
Develop and drive standard cell development activities for test and production chips owned by the Advanced Development team.
Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new circuit design methodologies.
Ph.D. degree in electrical engineering or related discipline. Exceptional candidates with a Master’s degree with also be considered.
Experience in driving new standard cell circuit design concepts, modeling, simulation and layout optimization efforts to improve PPA.
Experience in developing low power custom circuits on advanced FinFET process nodes with Cadence tools and scripting languages.
Experience in developing new circuits and transitioning those to production is highly desirable.
Experience in library characterization flows, custom layout design, post-layout simulation would be an added advantage.
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Lee Shiow Chyn