The SPOT Low Power Engineer (SLPE) will drive power related activities for company’s next-generation products. This will include pre-silicon power modeling, power estimation, post-silicon power correlation and power reduction. The SLPE will work closely with other members of the Advanced Development team and the broader engineering community to develop ultra-low power design methodologies, test them out, and then deploy them in test chips at 12nm and beyond. The SLPE will also work closely with the Engineering team to transition new low power methodologies to support production chip development.
This is a “hands on” position that requires significant independent work and extensive cross-team collaboration. The successful candidate will be comfortable working both independently as well as in a leadership position collaborating with a variety of senior engineers. The successful candidate will also be comfortable with the uncertainty that comes with new methodology development and will have a strong sense of independent drive.
Work with System, Architecture and Product Planning team to build and own pre-silicon power modeling, power estimation and post-silicon power correlation. Work closely with the Engineering team to track RTL and gate level power changes during project execution and co-ordinate with design engineers and architects to deploy low power design methods for power reduction.
Investigate, plan, and test sub-threshold and near-threshold design methodologies and other related low power techniques for power optimization (e.g., customized standard cells, level shifters, retention flops, multi-bit flops etc.
Validate and refine new low power design techniques as part of a team that is building complex test chips in advanced nodes (e.g., 12nm and beyond). Maintain a relationship and collaborate with 3rd party CAD tool vendors and foundries during the development of new methodologies.
A master’s degree in electrical engineering or a related field is required.
Experience in pre-silicon power modeling, analysis, and power reduction, with proficiency in PTPX, Power Artist, or other power analysis tools and post-silicon power correlation
Strong understanding of Low Power design methodologies, CPF/UPF, good understanding of physical design flow and timing closure with actual implementation experience as a plus.
Experience developing new methodologies and transitioning those technologies to production is highly desirable.
Knowledge in system architecture and SOC components such as CPU, fabric and peripherals
Experience in system and on-die power integrity and EM would be an added advantage.
Proficiency in scripting languages such as Shell, Perl or Python. Possess strong problem-solving and analytical skills.
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Lee Shiow Chyn