The Staff Physical Design Engineer is responsible for all phases of the physical implementation of complex modules in advanced process technologies from RTL to GDS, emphasizing synthesis, floor-planning, CTS, Place & Route, timing closure, power analysis, power grid analysis, and physical verification. In addition, the Staff Physical Design Engineer will be responsible for optimizing the designs for efficient power by developing custom low-power methodologies and supporting a unique ultra-low-power CAD flow for Ambiq’s SPOT Platform.
Physical implementation of complex modules/top level from synthesis through place & route for an ultra-low power SoC based on subthreshold operation using standard EDA tools
Achieve timing closure in Ambiq’s low-power designs
Analyze power and implement changes to reduce power
Analyze EMIR and implement fixes to meet the requirements
Perform physical verification of the module
Work closely with the digital design team in specifying power intent, timing constraints and addressing critical timing paths
Work closely with the digital design team to establish best design practices for clock generators and other elements that require close interaction with CAD tools
Explore the development of custom low-power methodologies both internally and in partnership with 3rd party tool providers
BS/MS in ECE/EE and 5-8 years of experience in the physical design required
Experience in all phases of physical design (module and top level) from synthesis to place & route to physical verification.
A deep knowledge of low power CAD techniques is extremely important.
Programming proficiency in Perl and TCL
Extensive knowledge of timing concepts and constraint development
Skilled in all phases of physical design: synthesis, floor-planning, clock tree development, placement, and routing
Understand power analysis, power calculations and low power techniques
Experienced with power grid analysis
Broad understanding of timing closure techniques
Experienced with the use and development of CPF/UPF files is a plus
Capable with physical verification tasks
Expertise in RTL synthesis
Motivated, self-driving engineer with attention to detail
Knowledge of the Cadence tool flow is a plus
Experience maintaining and supporting custom standard cell and I/O libraries is a plus
Strong verbal and written English communication skills
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Lee Shiow Chyn