As the Staff FPGA engineer, you will drive the FPGA/Emulation platform creation to support Design Verification, Validation, Software Development and System Test at the pre-silicon phase of SoC design.
This role will work within the Software & Solutions team and closely with the SoC Design team, Design Verification, and Validation teams.
The successful candidate will be highly self-motivated, results-driven, and a good communicator. He should be a good team player and be able to take the lead role for FPGA emulation tasks among multiple functional teams.
The person will be responsible for all aspects of the SoC emulation, from building and maintaining a complex emulation environment, mapping RTL design to collaborating with other engineers on hands-on debugging MCU design issues.
Work with software and design teams to understand the functional and performance goals of MCU design;
Follow the FPGA/Emulation process flow and platforms across multiple pre-silicon design projects while working with Emulation team members across multiple geographies;
Implement and debug FPGA design primarily on Stratix-10 development board using Quartus;
Assist software and validation teams in reproduction, triage, and debug of issues;
Support a regression test suite consisting of system-level test cases to validate updated FPGA builds.
BSEE or BSCE with 5+ years of SoC design, verification, or related work experience and 2+ years of experience of FPGA design, bring-up, debugging, and verification;
In-depth knowledge of top-down FPGA development process with recent experience with FPGA-based prototyping on a platform comprising one FPGA;
Expertise in Intel Quartus Prime Pro or Xilinx Vivado suites with emphasis on Quartus Prime Pro 19.x and later;
Solid understanding of the tool flow from RTL to bitstream;
In-depth experience writing Verilog code and FPGA timing analysis;
Familiarity with source code control systems (git) required;
Familiarity with languages such as C/C++, Make, TCL, Python script is a plus;
Familiarity with embedded systems and interfaces such as I2C, SPI, MSPI, UART, USB, SDIO, MIPI is a plus.
The above information on this description has been designed to indicate the general nature, and level, of the work performed by this position. It is not designed to contain, or be interpreted, as a comprehensive inventory of all duties, responsibilities and qualifications required.
We invite interested candidates to write-in with CV and regret that only shortlisted candidates will be contacted for a discussion.
Lee Shiow Chyn